The performance of very large scale integration (VLSI) systems has been improved by designing hardware that can handle greater clock frequencies. Since pipelined data processing systems generally use clocks which are generally a pair of differential symmetric clocks generated by a centralized clocking circuit, the skew and the rise/fall times of the clocking signals need to be well controlled. If the skew is large, slow or mismatched clock signals can result. This causes errors in the pipeline. Such errors are herein referred to as clock signal races and may be characterized by pipeline situations in which data in one stage "sneaks" through to a subsequent stage before the proper clocking signal is received. These "sneaks" cause lost data.
Top prevent these errors, conventional techniques may use differential clock signals in which one clock signal has a rising edge which occurs after a falling edge of the other clock signal and a falling edge which occurs before a rising edge of the other clock signal. Such signals prevent clock signal races in a pipelined circuit by deactivating a subsequent stage before data is allowed to propagate through the current stage. While such a clocking system prevents data from "sneaking" through to the next stage, it does so at significant performance cost due to the "dead" time between clock edges.
Global overlapping clocks may provide timing advantages with respect to non-overlapping clocks in that there is no dead time between a falling edge of one clock signal and the rising edge of the other clock signal. As a result, early clock edges may be received which allow improved system performance of the pipelined circuits. Global overlapping clocks may be easier to distribute to the circuitry without closely controlling the clock skew caused by time/phase shifts. However, as just noted, if the clock skew is large, race conditions may be created which may cause information to be lost when only global overlapping clocks are used for clocking the pipelined circuits. Furthermore, global overlapping clocks require the distribution of two clock signals. The distribution of two signals instead of one requires extra resources. Finally, the clock skew caused by time/phase shifts of the global overlapping clocks increases the amount of dead time necessary. As the dead time increases, it reduces the amount of time available for other circuitry to do its job. This cuts performance.